1. Field of the Invention
In general, the present invention provides Static Random Access Memory (SRAM) cells. Specifically, the present invention provides eight (8T) and ten (10T) transistor SRAMs that isolate read and write paths through the cell.
2. Related Art
Current 6T SRAM cells suffer from read operation instability caused by random mismatch in threshold voltages (Vts) between adjacent devices. A dopant implant is often used to set the activation threshold of a Metal-Oxide Semiconductor (MOS) transistor. The total amount of dopant implant is a function of the area under the gate of an MOS transistor. As technology scales down, the area under the gate of the MOS transistor is reduced so much that the number of dopant atoms becomes a statistically significant variable, and can cause large random mismatches in activation threshold voltages of neighboring devices. FIG. 1 shows a conventional 6T SRAM cell 10. During a read operation of a conventional SRAM cell 10, the bit line BL and the bit line complement BLN are initially pre-charged to VDD and then set into a high impendence state. The write line WL is then activated and the pass transistors N3 and N4 are turned on to sense the state of the storage nodes S1 and S2, which act to discharge either bit line BL or BLN depending on the stored state. If storage node S1 is at a low state and N1 has a abnormally high VT caused by random dopant implant fluctuation, and N3 has a low VT also caused by a random dopant implant fluctuation, the charge on the bit line BL could cause node S1 to rise high enough to flip the state of S2 before it is sensed. This will cause the circuit to fail and lose its proper state. Other combinations of threshold voltage mismatch and operating point mismatch can cause similar read mode failures in a conventional SRAM cell. A problem with the conventional cell 10 is that during a read operation, the storage nodes S1 and S2 are directly coupled to the bit lines BL and BLN, and thus are susceptible to charge sharing effects. For the conventional 6T SRAM cell 10, allowing longer read times would not help correct the stability problem since the bit has already failed and has lost any stored data.
Another common problem of 6T SRAM cell 10 is the “false” read during write operations that can be exhibited. This is demonstrated in the graph 12 of FIG. 2. Among other things, graph 12 demonstrates the effects when a write signal arrives later than a word line. In addition, a large number of cells on bit lines can lead to read instability. The optimization of pass gate device parameters for the conventional 6T SRAM cell 10 of FIG. 1 is always a fine balance between performance and the stability as the read/write is done through the pass gate. As a result, minimum voltage (Vmin) of the 6T SRAM cell 10 may be limited. Still yet, read or write operations can be done in only one cycle.
In view of the foregoing, there exists a need to solve at least one of the deficiencies of the existing art.